1. Field of the Invention
The present invention relates to a printed circuit board having land arrays to which solder is applied by flow soldering when an electronic part, in particular an element having plural terminals aligned in a line like an IC, is mounted thereon.
2. Description of the Prior Art
In the case of a land array for multiple terminals on a conventional printed circuit board, on which a surface mount IC element having plural terminals aligned in parallel is mounted by dip soldering, the length of the exposed portion, not covered with a resist, of each land has heretofore been identical. As a result, when flow soldering is applied, solder is likely to spread excessively at the backside, in the direction of flow, of the land array for multiple terminals and there is a tendency to form a solder buildup and cause short-circuiting between terminals.
With regard to the problem, Japanese Unexamined Utility Model Publication No. 038663/1991 describes the technology that reduces the amount of solder buildup at a land having a reduced width by: forming a land the width of which reduces as the distance from the front end of the land increases toward the backside of the land in the direction of the flow of flow soldering; further forming a dummy land acting as a solder reservoir in the vicinity of the back end of the land; and thereby making use of the surface tension of molten solder.
Likewise, JP-A No. 290065/1998 describes the technology that reduces the amount of a solder buildup by: disposing a dummy land at one side of a land relative to the direction of the flow of flow soldering; connecting the dummy land to the land at the back end thereof in the direction of the flow of the flow soldering; and thereby making the dummy land absorb molten solder through the connection.
Further, JP-A No. 142810/2003 discloses the technology that makes short-circuiting hardly occur between terminals by: connecting the land, in a land array for multiple terminals, at the back end in the direction of the flow of flow soldering to a dummy land disposed on the backside of the land in the flow direction through a constricted portion; and making it difficult for the solder once introduced into the dummy land during flow soldering to flow back by the hindrance of the constricted portion.
Furthermore, Japanese Registered Utility Model No. 3088837 discloses the technology that makes short-circuiting hardly occur between terminals by means of: forming the land, in a land array for multiple terminals, at the back end in the direction of the flow of flow soldering so that the width thereof may be wider than those of the other lands; and dividing with silk the land of a wider width into two sections in the direction perpendicular to the direction of dipping.
However, there have been the following problems in the prior technologies explained above.
In order to solve the problem of solder buildup formed on the backside in the direction of the flow of flow soldering, in the above prior technologies, a dummy land is disposed in the vicinity of the relevant land where solder buildup is anticipated and the dummy land is used as a land for a solder reservoir to introduce excessive solder.
In the case of a land array for multiple terminals which is used for surface mount and tends to form solder buildup, since the spaces between adjacent terminals are narrow, it is not practical to adopt the technology disclosed in the aforementioned document of Japanese Unexamined Utility Model Publication No. 038663/1991 or JP-A No. 290065/1998, wherein each land is provided with a dummy land. Further, when the technology described in the aforementioned document of JP-A No. 142810/2003 or Japanese Registered Utility Model No. 3088837 is applied, a space for the disposition of a dummy land or the like is inevitably required at the back end, in the direction of the flow of flow soldering, of an aligned land array. In addition, in the case of disposing a dummy land only at the back end, accumulated solder cannot be absorbed sufficiently in some cases.